1. Technical Field
This disclosure relates to microprocessors, and more particularly to load and store operation ordering and speculative execution.
2. Description of the Related Art
Modern out-of-order processors are often configured to execute load and store instructions out-of-order, and also permit loads to access memory in a speculative manner. Speculatively-executed loads and stores are typically held in queues until necessary criteria is met to make the loads and stores architecturally visible (i.e., visible to software). In a multi-processor environment, the ordering rules of memory accesses by various processors is defined by the memory consistency model specified by a given instruction set architecture (ISA).
In addition, many ISAs support event-based instructions such as the Wait for Event (WEV) and the Send Event (SEV) instruction pair, for example. The WEV instruction may allow a processor to suspend its activity and possibly enter a low power state while waiting for an event generated from outside the processor. The SEV instruction allows a processor to generate an event and have it sent to all other processors in a multiprocessor system. The waiting processor may awaken upon receipt of the event generated by the SEV instruction. In out-of-order processors, it may be possible for a load that is younger than the WEV instruction to speculatively execute. However, because the WEV and SEV instruction pairs are not typically governed by any shared memory ordering rules, they require barrier instructions if they are to be ordered with respect to loads and stores. However, barrier instructions are not an efficient way to try to, nor can they necessarily guarantee the ordering rules have been followed.